History of Athlon 64

All of the 64-bit processors sold by AMD so far have their genesis in the K8 or Hammer project.

The Athlon 64 was originally codenamed ClawHammer by AMD,^[3] and was referred to as such internally and in press releases. The first Athlon 64 FX was based on the first Opteron core, SledgeHammer. Both cores, produced on a 130 nanometer process, were first introduced on September 23, 2003. The models first available were the FX-51, fitting Socket 940, and the 3200+, fitting Socket 754.^[6] Like the Opteron it was based on, the Athlon FX-51 required buffered RAM, increasing the final cost of an upgrade.^[7] The week of the Athlon 64's launch, Intel released the Pentium 4 Extreme Edition, a CPU designed to compete with the Athlon 64 FX.^[8] The Extreme Edition was widely considered a marketing ploy to draw publicity away from AMD, and was quickly nicknamed among some circles the "Emergency Edition".^[9] Despite a very strong demand for the chip, AMD was plagued by early manufacturing difficulties that made it difficult to deliver Athlon 64s in quantity. In the early months of the Athlon 64 lifespan, AMD could only produce one hundred thousand chips per month.^[10] However, it was very competitive in terms of performance to the Pentium 4, with magazine PC World calling it the "fastest yet".^[11] "Newcastle" was released soon after ClawHammer, with half the Level 2 cache.^[12]

On June 1, 2004, AMD released new versions of both the ClawHammer and Newcastle core revisions for the newly-introduced Socket 939, an altered Socket 940 without the need for buffered memory.^[13] Socket 939 offered two main improvements over Socket 754: the memory controller was altered with dual-channel architecture,^[14] doubling peak memory bandwidth, and the HyperTransport bus was increased in speed from 800 MHz to 1000 MHz.^[15] Socket 939 also was introduced in the FX series in the form of the FX-55.^[16] At the same time, AMD also began to ship the "Winchester" core, based on a 90 nanometer process.

Core revisions "Venice" and "San Diego" succeeded all previous revisions on April 15, 2005. Venice, the lower-end part, was produced for both Sockets 754 and 939, and included 512 KiB of L2 cache.^[17] San Diego, the higher-end chip, was produced only for Socket 939 and doubled Venice's L2 cache to one MiB.^[18] Both were produced on the 90 nm fabrication process.^[19] Both also included support for the SSE3 instruction set,^[20] a new feature that had been included in the rival Pentium 4 since the release of the Prescott core in February 2004.^[21] In addition, AMD overhauled the memory controller for this revision, resulting in performance improvements as well as support for newer DDR RAM.^[22]